my name is
michael stairs and professor at the key loving
and I'm going to teach the next few lectures
in this course
we will see different topics such as ada converters
but also interference effects and pale circuits
I hope you will learn something in those courses
good luck
welcome to the lecture
deep supermarket and low voltage
two words
unwind volt and low integrated circuit design
in this lecture
we will give an overview
of the trends towards deep submarine and low voltage
integrated circuit designs
and certain problems related to that
several topics will later on in the course
discussed more in detail
so it's a kind of overview and introduction
of this course
it's clear
that the trance is that we are going to deep soup
mi nanometer technologies
and we have seen that over the years
what you see over here is an
itu police spectrum
paper
off about 30 years ago
where we can already see the trends or we could see
already the trends
that we were going to extremely low voltage
applications
and indeed over the years
the voltage
and the transistor lengths have become smaller
and smaller
today we are talking about deep nanometer technologies
soup
ten nanometer technologies are already on the market
and this search is going on two birds five
and even two nanometer technologies
what you see over here for example
is the trans two words
deep nanometer transistors on the left hand side
you see for example a thirty nanometer technology
what you see over here is already fifty nanometer
technology
these are still based on the classical technology
using most transistors
gate and oxide techniques
an important thing to remember
over here
is that the oxide thicknesses of those transistors
are becoming extremely thin
typically the oxide thickness is in the range of point
eight nanometer or even less
and that means that we are talking about
several atom layers
that means that if you're going to
even deposit my biotechnologies
some issues can come up
especially the breakdown voltage
and that is reason why we go to
extremely low voltage or so point volt applications
a thing that you have to remember
and that's the reason why I show microphotographs
and it's quite important
for the whole course
is what you typically do not see on the slide
but you do not see on the slide
for example is the drain area
or the source area of that transistor
and as you will see later on
this will become extremely important
for unlock circuit design
it's deep submission technology something new
what you see over here is the paper of about
30 years ago
93 where they already presented
nanometer technologies
again what you should see over here
in the pictures
is that they are able to make indeed intrinsically and
very
small transistor
but what is important to notice
is a huge area that is still required
in the drain area and the source areas
try to remember as aloe designer
these type of things will become very important
of course one of the advantages of going
to deep submarine technologies
and nanometer technologies
is that of course the ft of the transistor
can be increased enormously
is that something new again
what you see where he is a paper of
more than 30 years ago
where in bipolar
they were already
able to achieve 600 he heard f ts again
what you should notice
is that we have a small transistor
so the intrinsic transistor is very small
but look to the area of the collector and the base
and this will result for analog circuit design
in some issues
of course there is a lot of research going on
in exploring towards deep and nanometer technologies
for example what you see over here
is the use of so called notables
by using a mano tube
we are able to make transistors
over here you see the source
the drain and the mano tube
and again one of the major problems of this type of
techniques is
the ability to arrange
the nannette and result is that you need a large
area for the source and the train
with this type of transistors you're able to make
n and p most transistors assault it is
you're able to make inverters so you're able to make
digital circuits
but again due to the
lot of area in the drain and the source areas
the speed performance of those
technologies are extremely bad
what is the trends
the trends is of course that we are going to
deep suit micron and nanometer technologies
and what you should notice is that
over the years indeed
we are going to deep some mic on technologies
and usually the technology is driven by memory business
because there you really need a very compact
integrated circuit design
a few years later
typically
the deeps of micron is so that the technology
is achieved in the digital circuit design
and then in other few years later
those technologies
are becoming available for analog circuit design
however what we see over the years
is that the more we go to nanometer technologies
the distance
in that technologies are becoming available
for analog or for memory
or becoming shorter and shorter
and the reason
for that is that we're going to very high speed
circuits both for memory and for logic
and that means all kind of
analog problems are popping up
also in those type of technologies
and the big witnesses
at the end of the deep submission technologies
are the analog circuit designers
because they can benefit from those
new technologies
if you scan the open literature
you will see that there is a lot of discussion about
the so called end of the shrinking
are we really going to nanometer and sup
the nanometer technologies
what is important to notice is that indeed
the gate length
the interesting gate length is slowly saturating
but what is important to remember is that
also the pitch in
metal stacks are become smaller and smaller
obit words and that's an important message
for the cars
is that we should not
only look to the minimum feature size of a transistor
but we also should look to the other
features in the technologies
for example the number of metal tracks available
the number of metal pitch the width of the metal
which can be achieved in the technology
as you will see later on
this will become dominant for
hand circuit design
and especially for ad and high speed ad and di
circuit designs
since the fact that we have a kind of flattening out
of the intrinsic
gate length you see indeed
the discussion popping up in the open literature
the so called end of the shrinky
some foundries for example global foundries
announce few years ago
that they will stop
doing research towards even deep submit technology
the question is
will
deep suit micron become available
the trance is for sure that we see new
techniques popping up in order to go to
deep nanometer technology
to so called fin fat technologies
as you probably know
some big companies until dsmc etc
or offering now these fin fat technologies
the big difference is that
instead of the most transistor in
the planet area we are going to make now
most transistors around
a thin as they call it
and as a result we are able to go to
deeper zim michael technologies
on the right hand side you see again
microphotographs of the fence over here
showing that we are able to go to
deeper nanometer technologies
but again and that's the reason
why I'm showing all those microphotographs
and this introduction
is be careful
indeed we are able to come to intrinsically very small
gate lengths in the transistors
but remember
that we end up with a lot of overhead
in the sources
the drains and the gates of the transistor
and that will of course affect enormously
the performance for analog circuit design
and this is already what I said several times
what is not on the photo
what you see over here is again
a microphotograph of infant
thin oxides thin
dimensions for the monstrous
but what is not on the photo
or the microphotograph is of course
the drain area and the source area
and you see it indeed popping up in publications
what you see over here is publication
from jerk where they analyzed
the speed performance of southern systems
and
what you should see is that it has a big difference
between what is called
intrinsic behavior of the most transistor
so that means this part over here
and the total behavior of the transistor
including the parasitics
and what you should see is that
if we go to deeps michael technologies the
extra effects of the source during interconnections etc
becomes more and more important
or with other words intrinsically
we have very good transistors
but due to the fact that we have to be
able to connect or strong systems to the external
world or the next circuits
you will see some interference effect
you will see some
resistance effects coming in
you see some parasitic capacitance coming in
and result of that is that the performances are
not achieved at all
and that is one of the
important messages that I'm trying to bring
in this lecture over here
so yes we are going to deep super mic on technologies
but be careful
especially once you go to circuit design
and especially to unlock circuit design
that you have to be very careful with
the extra of external components
the interconnections
the drain areas
and the source areas of the transistors
I'm going to repeat that many times during the course
that you have to be very careful with your source area
and drain area
since they really
start dominating the performance of your circuits
on top of that
once we go to finn
fat and even deep suit mic on technologies
you will see
also some other technology effects pumping up
in the early day
the orientation
of how that we
designed or must transistors on the chip
compared to the flat size of the wafer
was not important
but what you see today
by going to deep semicon technologies
the performances can be affected
by the orientation of the moss transistor
and it's not
only for the speed performance
what you will see in these graphs over here
but it is also for
which I will discuss later for the matching performance
that means that the dsu's esu's
will become more complex in the future
and that the design and the correct
symmetry and layout of our transistors will become
important to achieve the performances again
you will see that during the course
I'm going to repeat that many many times
symmetry symmetry symmetry matching in the device
is important in order to achieve the performance of
high performance ada converters
more complex rules orientation will become important
in the future
but as you probably know
fin is one technology but today
a lot of research is going on
in the so called nano sheet
technologies
so we had the planet technologies typically limited
down to let's say twenty nanometer
fifteen nanometer technologies
then we have seen the fin fat technologies
but also there
we see some problems popping up if we try to go to
small feature sizes and for that reason
they have developed the so called nano wires
and even the nano sheets
or also called gate all around the moss transistor
the big advantage of this type of
technologies
nanon technologies is that we are able to go to
deep nanometer technologies
five nanometer and recently
even
two nanometer technologies have been announced
now another big advantage of
the nano sheet and especially if you go
from anoints towards nano sheet devices
is that you can size your transistors
and that was one of the problems in the finn fats
in a finn fat structure
basically your moisturizer is fixed
you have very
few
design freedom over there
and that's a big advantage
if you go to non or sheet devices
or without words the dimension the width of the device
can be designed by the designer
and the result is that you can optimize the structure
or that you can
achieve better
performances
depending on the requirements of your components
and your performances
and that's one of the big advantages
towards your future
of nano sheet transistors that we again as design
have some design freedom over here
the discussion that pops up in the malachi chair
fin faces nano sheet
towards deep submission or deep nanometer technology
and again it has a lot to do
with the external interconnections
between
finn fats and nano wires
and the fact that in nano warriors
you are able to perform better connections
what you will see is that if you go to
deeper nanometer technologies
the performances of
nan wise or nano sheets are doing better
than the final technologies
for that reason
I am a believer that
towards the septa nanometer technologies
the nano sheet
will become quite popular since we are able to
do sizing of the transistors as well
on top of that
and that is what you also see popping up in recent
publications
is that in a nano sheet devices you can do
stacking of transistors
you are able to do
a stacking of transistors on top of each other
and the advantage of that is that you're able to go to
more and high
dense layout or without words you're able to achieve
better
small chip area or better performances
you can go even one step further
and that is what we have seen
very recently in publications
where they interviews introduce so called
animals palms stacking in a nano sheet wires
meaning that you have the
po doped transistors
and the animals doped transistors on top of each other
and the big advantage of that is that you can make
as such
logic circuits
for example an inverter can be realized
by using stacked topologies
meaning that we are able to come to come to even dancer
circuit designs
less preceding capacitances and as result
higher performances
so nano sheets
seems to have some potential towards the future
certainly by using stacking techniques
but also by going to deep nanometer technology
probably know that ibm recently announced at sub
ten nanometer sub two nanometer nano sheet devices
for that the chance
is that we go from planner technologies
typically down to twenty nanometer nanometer
below 10 enemies we see the fin fats popping up
but in my opinion
soon we will see that the fin fats will be replaced
by the gate all around
nan wires or nano sheets
the big advantage is stacking
and the fact that you are able to go to
deep nanometer technologies
that brings us to the next
trans integrated circuit technology
and that is the dominant market of demos technology
what you see over here is the market
or the percentage of
integrated circuits
compared to the different technologies such as bipolar
biomass
se and other technologies gallium indium phosphide
et cetera
what you should see is that the market today is
totally dominated by se technology
and the main reason for that is of course the costs
seamless technology
this area is quite cheap compared to
bipolar gallium or other technologies
and that is the main driving force
and that is the main reason
why seamus is so published
and that is the reason
of course in this course
that we will concentrate on how to design
high performance
add and converters in demos technologies
sometimes it's funny to notice
the cost of seamless technology
compared to for example real estate area
and you see that is more or less the same price
you can ask yourself where should we invest in anyhow
se is very cheap and as a result
the market is dominated by that
what about going to deep semicon technologies
well as we can
expect is that
the deep name technologies
will become more and more important
towards your future
if you can believe this paper over here
the four courses is that
25% of the market
will be in 23rd
in twenty twenty three twenty twenty four
will be dominated by the
deep nanometer so less than nanometer technologies
what we see is that year of the year
the soup
nanometer so levant nanometer is increasing enormously
of course this has a lot to do with cost issues
and that we are able to integrate more on a chip
and that's also a big advantage of the nano sheet
a topology because you can do stacking
and as result the area
of the chip becomes smaller and smaller
and this is also more or less more slow
namely that over the years we see
every year that we are able to integrate more
on a chip
and that we go to small dimensions year of the issue
although the low it's not a physical low of course
the practical low what we see is that
it is slowing down a bit
in the early days
it was doubling every year
today the doubling is
every one and a half to two years
so there is a kind of slowing in the more slow
better trans
to deep zip mic and deep nanometer it goes on
and it has had
in the past some quite important impact
on circuit design
for example if you look back to 2030 years ago
in rf circuit design
mobile telephones etc
what we have seen is that all circuits
before the year 2000
were basically bipolar technologies
in the early days bipolar was
technology for rf circuit design
but what we have seen in the nineties
is that due to the fact that we are going to deeper
and deep into
micron technology
that
the research and improvement in those technologies
was much much faster
much much faster than the bible technologies
and what does that mean
that means at a certain moment
and that happened in the beginning of the nineties
that suddenly simos was performing
better in ft performances than bible of technologies
and that is the reason why you will see that in
the nineties
there are a lot of papers popping up
about rf circuit design
because suddenly
we were able to do rfc moss circuit techniques
of course in the beginning because this is a
platform idea
what we present over here is one working transistor
it takes some time before you have
circuits typically five years and it takes some time
typically 10 years
before you have commercial products
and that's exactly what we have seen
10 years later the year two thousand two thousand ten
in that period
we have seen a lot of products popping up in rfc moss
but of course in bible area
they did sort of improvements in technology
by introducing the so called solution germanium
the result is that that the rut curve was shifted
upwards and that means that
we see the crossing of demos again five years later
and again
that means rfc moss products commercial products
typically five years later
around the year 2010
today I'm quite sure if you open your mobile phone
it's full of rfc mo's circuits
thanks to the fact
that we're able to go to nanometer technology
we are able to go to very high speed
very high fits and a result rfc moss is now
dominating the market
but there is a drawback related to that
and one of the drawbacks is that if you look back
30 years ago
we were using typically power supplies
five fold 12 fold
even 15V
and these bomber supplies were
more or less constant over a long period
but that at a certain moment and that happened around
0.5
micron technologies to deep submit technologies
what happens is
is that
every time that the new technology came on the market
the power supply of the circuits were dropping
roughly speaking
point twenty five
gives you 2.5 fold
0. one eight gives you 1.8 folds
roughly speaking
but if you do that interpolation
you will see immediately that we will end up
in a serious problem
if you go to nanometer technologies
that means that we should
end up with power supplies
less than one vault
and that will result in a lot of problems concerning
matching which I will discuss later on
but also in a lot of problems concerning norse
single to norse ratio in analog secrets
and as you will see for a tod converters
this becomes quite important
because we are off the high
single to north ratios in this type of building blocks
for that reason
we will discuss deeps of micron techniques
we will discuss
low voltage techniques in order to overcome
sampling devices in a to d converters
but try to remember
we are going to
deep nanometer technology
and the result of that is that we are also going to
low voltage applications
a second reason why
cmos is taking over in the rf area
has something to do with the ft and the f max
you probably know that the ft is a
parameter for a speed in small single behavior
f max is more a parameter
for the maximum power that can be delivered
by a certain device
and what you see on the left hand side is
the performance of the ffdf max for bipolar transistors
as function of the minimum feature size
in this case it is plotted as function of
the breakdown voltage
but that's the same
the low breakdown voltage the lower feature size
and what you should see is indeed if you go to
minimum feature sizes deep submission in bipolar
dft is indeed becoming better
but what you should also see
is that the f max or the ability to deliver power
is dropping down
and that is the reason why
most technologies in bipolar are designed
in some way of the crossing
between the ft and the f max
and that is very often called the johnson limit
but what you should
see is that we end up in metabolic with an
interesting problem
if you go to deeper nanometer technologies
we will end up with problems with power delivering
and that's a big difference with sims
if you go to nanometer technologies again
it is spotted as function of the breakdown of voltage
but that means deep soup michael technologies
again the ft is going up as can be expected
but what you
also should see is that the f max becomes better
and better
and that means also for
building blocks where power is important
for example d a converters
for example power amplifies in our f circuit design
seam will take over the bipolar area
due to the fact that we are able to go to
nanometer technologies
and that we are ending up with better
f max performances compared to bipolar technologies
you can even design technologies but they are not that
much available
but you are able
even design technologies for better f max
for example by using t gates
basically they try to reduce
the resistivity in the gate
by putting a big metal chunk on top of the gate
and in that way you're
able to improve the f max performance
in the transistors
but again these type of technologies are not popular
but it is at least possible in seamless technology
now of course
you may not forget that
we do not talk about one transgresses in circuits
at the end we are talking about many
circumstances integrated on one chip
and that means that
also the input output count becomes quite important
what you see over here is the trans to
the number of pins that is coming out of modern diction
circuits
pin counts of who over 1000 are not
uncommon anymore
meaning that interaction between the external world
becomes quite important
try to remember that
for the last t so the third t in this course
we will try to discuss the interference effects
due to the fact that you go on and off j chip
this becomes quite important
for high speed digital and unlock circuit design
since that we are going to
quite big
digital circuits with a lot of interconnections
pint count is a cost
but
the result of that is that we have to be very careful
in the design
especially towards interference effects
and that is also one of the reasons why we have seen
that the clock speed of
digital circuits are
not improving anymore
again if you look to the history
you see that of the intel processor for example
the clock frequencies where going up and up
even internally up to 10 heads
but what we see nowadays is that
the clock frequencies are not improving anymore
due to the fact that a lot of
performances are limited
due to
the source areas the drain areas due to the parasitics
and what you see now
since it's the fact that some technology is very cheap
that we end up with multicore topologies
course in the range of eight
sixteen twenty four and thirty thirty two
course are nowadays not uncommon
and a result of that is that
you see that they try to use
the fact of the cheap technology by implementing more
chips on an integrated secret
instead of going to higher frequencies
they are going to multi core topologies
what you see over here is in 48 core
prototype until a processor already presented
about 10 years ago
of course one of the drawbacks in this type of things
is that we will end up with a lot of
power doing in those circuits
what you see over here is an ibm
power in
digital circuit
a dual core in an nanometer technology
running at five high arts var power supply
consuming about her not what
and that is typically modern microprocessors
consume typically around her network
in deep nanometer technologies
with what you should remember
is that the power supply in those circuits
today are in the range of one vault
and I'm quite sure you all know home slow
hundred want one vault
that means that we are dealing with hundred amps
huge currents
and that is the reason why
multi metal layers are required
and that we have to be very careful
as we'll discuss later with so called
power management
electromechanics
thick metal is enough technologies in order to avoid
to handle the high currents in those technologies
the bower density
the current per density becomes also an issue
and that is also what you see happening over here
the cooling of those chips becomes more and more
an issue
as already mentioned
we are going to deep michael technology
and you can ask yourself
what are the limitations
and what are the problems
if you go to deep michael technology
and on the left hand side
you see a very simple schematic of an
oppression amplify defection pair with a gun mirror
and on the right hand side
you see a simple digital building block in inverter
and you probably know that in an
amplifier we have to make sure that the circuit
is stable that we have so called enough
face margin in the circuit
for that reason it is important
that we do analyze the second pole
or without words the internal pole of the circuit
the 2nd pool
is in this
simple circuit given by the transconductance
divided by two times the gate source capacitance
because you have two gate source capacitance
over here in the circuit
and this gives us the second pole or the
non dominant pole of the amplifiers
now it's important to notice that
this relationship
this part of the mathematical relationship
is basically nothing else than the ft
of the transistor
or without words in first order
the non dominant pole
is roughly given by the ft of the technology
divided by two
now in order to guarantee stability in the circuit
it can be shown
and will not show the mathematics over here
but it can be shown
that if you're after a face margin of 65
degrees face margin in an amplifier
that the gain bandwidth of the structure
should be situated at the second poll divide by two
or using this mathematical equation
that means that the maximum gain
bandwidth that you can achieve in a technology
is basically the ft
divide by four
what about digital circuit design
well what is important is the delay in the inverter
and the delay
has something to do with the gates source capacitance
of those transistors over here
and of course
the driving capability of the
mont sisters or the gm
or without the words the delay has
also something to do with the gm
and the gates or capacitance of those transistors
or with other words has
also something to do with the ft
of the transistor
typically a delay
is required in digital circuits
typically three times a time constant or without words
the high dft the low delay the better digital circuits
over the words
board for analog circuit design
and digital circuit design
the high dft the batter
and that is exactly the reason
why we are going to deep some microm technology
because if you look to the mathematics of the ft
you see that the length of the transistor comes into
the picture
and if we are able to
decrease the length of the transistor
sure the ft is going to increase
and the result of that is we are able to achieve
high performances
and that is the reason
why we are going to deeps of michael technologies
but as you can imagine
there are some issues popping up
in the early days
we were using
the first simple
square glow model for must transistors
for example if you look in spice
or the simulators
typically the spice level
one model is a simple square glow model
now if we take the derivative
of this mathematical relationship
then we have the so called transconductance
and what you should see is that transconductance is
dialed proportional to the vgs mining switch
and combining those two mathematical relationships
brings us to a quite important
mathematical relationship for halo circuit design
namely
data transconductance
is given by two times the bison current divided by
v mining sweetie
now the vgs minus t
has some limits so if you make
vs minus v too small
you will end up in so called making version issues
for that reason
typically the minimum vgs minus fit that is required
is around a hundred fifty two hundred millivolt
the so called boundary of storm inversion
and if you use
over here
200 milli volt as boundary
of strong inversion
so a vgs mine c of 200 milli volt
then you
hope that you see that
the relationship between the bison current
and the trans conducting
becomes a very simple mathematical relationship
and based on that
we can draw already some quite important conclusions
for example in polish
we all know that relationship
between the transconductance and the bison current
is 40 times the bison currents
in seam of technology it's only 10 times
that means that if you're
after extreme low power circuit design
your footage better have
by using bipolar circuit techniques
even in gallium r leonidas you can
write down those mathematics and you will see that
in gallium r leonidas
they typically they use the same automatic
but instead of vgs mining sv
they talk about pinch voltage
typically pinch voltage is around one to two volt
but as you can see immediately
that means in gallium arsenide
you end up with one to two times the rising current
for the transconductance
and indeed you will see that in gallium
they are able to achieve very high speed
but typically at the cost of a huge powered way
now luckily as already mentioned
if you go to very
small vgs minus fit in seamost technology
then you end up in weak inversion
and in weak inversion
the in seam of
relationship between the trans conductance
and the bison current
is approximately 30 times
or without words
it gives you already a very good hint
that if you try to go to
very low power circuit design
we should try to use
bipolar or some weak inversion
however if you're after speed
you will see that we work more
at the boundary of strong inversion
but that will cost us more polish
but of course
we are going to
deep soup micron technologies and you probably know
that those mathematic relationships are not
valid animator
if we go to deep soup micron technologies
and that has of course a lot to do
with the high velocity
saturations of the electrons at short channel effects
and as a result
and that is
reason why you see the new models popping up
sparse level
tree for 10 etc
the new models popping up including
the short channel effect
and high electric fields popping up
in
the transistor
and what you should see is that if you go to high
speed circuits
and if you go to
short channeling
so minimum feature transistor
deeps micron and nanometer transistors
this term becomes more important
and the result of that
is that this term is going to vanish
and that means that that term is going to vanish
and that we have a kind of saturation over there
and that is what they call the velocity saturation
and the only way
to overcome that is by using small vgs mining sets
but that means that
we will go from immediately weakened version
to velocity saturation
over the words
the square low relationship
will totally vanish in nanometer technologies
and this typically happens if you calculate that
with
technology parameters
you will see it happens
typically around a hundred nanometer technologies
so if you work
in deep nanometer technologies
so forty five twenty nanometer technologies
you will see that the square
low relationship of a monstrance
is totally vanished
and that basically we go from breaking version
basically to velocity saturation
and you can see that also
in the graph over here
so what is plotted in this graph
is this mathematical relationship
mathematically as function
the gm of the transcends as function of vgs mining ct
this is a weak inversion
this is a square low relationship
and this is velocity saturation
and basically what happens is
the boundary of storing inversion
is around 200mV
so vgs mining city of two hundred millivolt
and basically what happens if you go to
deeper submission technology
the boundary between
saturation a velocity saturation
is going to shift to the left hand side
and basically at a certain moment it will flip
over here or with other words
we go from weak inversion immediately
to velocity saturation
and that is basically what happens in
nanometer soup deep soup nanometer technologies
the result of that is also
that the ft of the transistor
will not improve anymore
as function of the length of the transistor
our little words
we will end up in a kind of flatting art
of the improvement
of the ft and that is also what we see happening
the ft versus technology note
if you go to deep supermarket technologies
you see that the ft is more or less saturating over
but it is more than high enough
to go to
rf applications and even millimeter wave applications
now it's important
to notice already mentioned that several times
that besides the intrinsic transistor
it's also important to discuss the area
the source area the drain area
and the price tickets effects
because if you
do the calculation over here
if
we have f t's of let's say 500
hill hurts 400 he hurts
divided by four
that should mean that we should be able to make
gain band of
hundred hill hurts
we all know from practice that
opens with a gain benefit of hundred hears
do not exist
and that is a reason for that
is because if you go to deep soup micron technology
this mathematical relationship is not valid anymore
or in other words
the mathematics is correct
but due to the high
velocity saturation ft is going to saturate
but also
the parasitic ball
is not only given by the gates or capacitance
it is
also given by the parasitic effects in the drain area
and the overlap capacitances into transistors
for that reason
we do have to discuss
the effect of the parasitics of the
drains and the source
and that's the topic that I would like to discuss
in this
few slides what you see
over
here is a cross section of a classical must transistor
the source the drain
and the gate
and of course
we then do have some overlap capacitance over there
now that overlap capacitance
is of course
a function of the width of your transistor
or without words then why do you make your transistor
the more overlap capacitance that comes in
typically that capacitance is given by how good
they can manage the overlap or minimize
overlap in the technology
so this is technology parameter
once you have selected your technology
this parameter is fixed
and of course
as function of the width of the transistor
now what I'm going to do now
is I'm going to introduce so called
alpha parameters
and the alpha parameter is the resume
of this parasitic capacitance
to the gate source capacity
and you probably know that
the gate source capacitor in a monstrosity
is roughly given by two thirds c low times l
now what is important
to notice is that if you use that in this mathematics
over here
I do hope that you see
that the w is finishing out in the mathematics
or without
if you calculate alpha parameter or the race
between the positive capacities
and the main capacitance
this is only given by technology parameters
this is a technology parameter
and the minimum feature size is
also a technology parameter
or with other words
once you have selected your technology
this parameter is fixed
for example
in an oldest technology a 0.7 technology
that alpha parameter is about 0.3
that means that if you design a transistor
minimum feature size transistor
you always end up
with a dirty %
parasitic capacitance in the overlap
capacitances
of course you can also
redo the calculation
for the capacity capacitance in the
drain bulk capacitance
the train built capacity is a function
of the width and what I call edge the minimum feature
to draw your contact holes
again a technology perimeter
is also function so that's given by the area
of the source and the drain
over here so the width
times at the minimum feature size to put contact holes
and the technology perimeter dimension
capacitance
and of course
also the side wall capacitor
now if you neglect this term
and we calculate the alpha
parameters to keep it simple again
you can come to technology independent
mathematical relationships or with other words
the parasitic capacitance is given by the minimum
etch in your technology
the oxides and the minimum feature sites
and the kingship capacitors per unit area
in your technology
to give you an id
in an all of technology 0.7 technology
this was already
1.4 or without words 140%
parasitic capacitance
for a given transistor
this should give you already an indication
that the parasitics drain
source areas are becoming very important
for circuit design
as our mentions several times
luckily we can do some tracks
and the first trick that you can use
is by using so called finger layout topologies
by using finger layout topologies
you're able to reduce the area of the drain
with the factor too
you can go even one step further
so called waffle layout structures
where you have the gate
four times around the drain area
resulting in four times less positive capacitances
this is bat for speed performances
I'm not going to discuss it further on
but this is bat for norse performances
the reason is that you have no bull contacts
and for that reason
this is also not so popular
and that's the reason
why the layout of this type of topologies
is very popular
because it's a good make sure
between speed performances and norse performances
and
for an older technology 0.7 micron technology
you see who hear
the different alpha parameters for the ant
monstrosities
the p motions
and the way of layout
so the straightforward layout
this layout the finger layout or the waffle layout
and what you should see is that
indeed we will end up with some
dominant parameters over there
especially in the pm of transistors
meaning that you have to be very careful
with your source and editing area
in circuit design
and to give an example
there is a big difference
between the ft of the transistor
and what we call the three db point
of a moss transistor
what you see over here is a must transistor
where we connect the gate with the drain
this is a very popular schematic
for example for current mirrors amplifies
and converters and so
very popular building block
drain gate connection
and let's now calculate the three db point
of this connection
the three db is given by the gm of this transistor
divided by two by the gates or capacitance
of the transistor
but you also have some drain
bulk capacitance popping up
and you also have some overlap capacitance popping up
and now you can rewrite the mathematic relationship
using those alpha parameters
and if you use those alpha parameters
you can rewrite the mathematical relationship
into the ft one plus those alpha parameters
and what is not the problem
in the old technologies
those parameters are not so dominant
and the result is the ft was the most
important pyramid
and that is the reason why you will see that
technology guys
are really optimizing the ft of the technology
because then we are able to achieve
high speed performances
but what you see is that if you go to
deep semicon technology
and especially if you go to
nanometer technologies
those parameters will become dominant
or in other words
we have to neglect that term compare to this one
and that means that the story totally reverse
meaning that the ft is now not the dominant
parameter anymore
but that the drain areas and the source areas
those parasitic capacities are becoming really dominant
you can see already that effect
even in old technologies
what you see over here isn't
the performance of a 0.7 michael technology
technology of 20 years ago
well already there we solve those effects
the ft of the technology for
transistor was 2.5 high arts
the tweedy b drops roughly with a factor
five to seven
down to 0.7 high arts
so you see that even in
all the technologies you see those effects popping up
and the problem of the parasitic drain source
area or the problem of the alpha parameters
is becoming tougher and tougher
if you go to deeper submit technologies
what you see over here
is the relationship of the
issue between dft and fb point
for different technologies
going to deep submarine technologies
and as you see in the early old technologies
it was mainly dft
today dft is much much high than the twiddy b point
the problem is
this is what technology guys are trying to sell
this is
what unlock circuit designers are confronted with
and you can clearly see there's a big difference today
over there over the words
be very careful by selecting a technology
do not go on the ft
but try to calculate or simulate
1st the tweedy b in order to
check the ability of technologies
and what you should see
also in this graph is that certain technologies
do have good performances
but other technologies have very bad performances
so there is a big difference
between let's say point twenty five
and a point twenty five
for the other company
everything depends on the parasitics
the drain areas
the source areas the interconnection over there
and as you can notice it becomes more and more
important in analog circuit design
so our summary for the moment
going to depth my biotechnology is nice
fine
we are going to deep nanometer technology find and
nan sheets
it drastically reduces
the size of the transaction
but we have to be very careful with the area
of the sources and ring
and that means more effect should be spent
in making the interconnections smaller
the gate drain
gate source overlaps smaller
and the auction capacitances smaller
this is very important
if you try to go to deep semicon technologies
those alpha parameters are becoming worse if you go to
deep suit michael
technology
but it's not only this
2nd problem that we are facing
is the so called vt shift
the problem is that if you go to
low vs we will end up in
problems of
leakage current and hot electrons
for that reason
in order to void
breakdown in the
oxide thickness
you see that if you go to deep submit on technologies
the power supply is going to drop
due to the fact that the oxide thickness becomes
finish and finish
in the early days we were using
10 vault power supplies
today in the nanometer technologies
we are typically using
wine vault or even below wine vault
however one of the problems that we are facing is
what about the vt to threshold voltage
if the threshold voltage is selected too low
then we will end up in leakage problems
on the other hand
if the threshold foldage is too high
we have no
volt vgs minus vt anymore because the voltage shops
and the result is that we really end up in a problem
in deep submarine on technologies
typically
the vt of all the technologies was around 0.7
vt of modern technology is around 0.5
or without words barely any change
while the power supply voltage dropped enormously
and the reason for that
has something
to do as already explained with the leakage currents
but also that we have to ensure that we are able to
guarantee
that the circuits work over certain temperature range
and of course
also due to the inaccuracy
in the doping of the technology
to adjust the threshold voltage
these are fundamental parameters
this is also fundamental fixed parameter
so the only parameter that technology guys can work on
is basically that parameters
and that's exactly what we have seen in the early days
the accuracy was less
today the threshold foldage becomes small
due to the fact that we have high accuracy
in the variation in the
threshold foldage
however
20 years ago
the result coltish was 0.6 to the
treasured volts is again around point six volt
all with other words the power supply drops
the result remains constant
we are in trouble
and you will see that
today in the last lecture
for that
we are going to discuss special techniques to overcome
this problem
so called switched open techniques
and you can ask yourself
why are we not using lower threshold voltages
well the reason for that is
if you go to lower threshold voltage
the leakage current becomes important
and the result of that
and that is what you see over here
from berkeley
that in digital circuit design
if your threshold folder is too low
the power drain
is mainly dominated by the leakage current
if the threshold folder is too high
the powered wind
in the digital circuits is merely dominated
by the dynamic performance
or the loss in dynamic performance
and result is that you need somewhere an optimum value
around two hundred millivolt again
two hundred millivolt
plus two hundred millivolt temperature
plus two hundred millivolt
variation gives us the six hundred millivolt
but what is important to notice
is that if you now go to
lower voltage applications
what you will see is that
the optimum value for digital circuit design
is that they will increase the threshold voltage
so that's not
in favor for out of circuit design on a long term
so basically what you see is that if you go to
deep or soap mic on technology
digital guys
will attempt to increase the threshold voltage
and result to avoid leakage problem
and result you will end up
with more problems in aloe circuit design
so the protection is that
in the beginning we will see some
shrinking or decrease in the traction voltage
but if you go to very low voltage applications
maybe the threshold voltage is going to increase again
due to the leakage problems in the digital secrets
hopefully we can solve that problem
by multi threshold technologies
using technologies
with different tv voltage available in the technology
but of course that means cost
2nd problem
by going to deep submarine transistors is a so called
gain that we can achieve
and that is of course important
if you try to design high performance amplifies
which is imported for
and converters
especially high performance seem adultery
at converters
the gain of a must transistor
the intensity gain of a must transistor
is given by the gm and the gods
and what you should see is that the
trans conductance
is given by the bison current divided by vgs minus pt
the gods in a
monstrosity in first order is given by the bi concord
and the so called early voltage and the length
or with other words if you use those mathematics
the gain is basically given by
this mathematical relationship
two times the early voltage
the length of tartans is a vgs minus fitting
again if you work out the boundary of strong inversion
this parameter is fixed to a hundred millivolt
early voltage is fixed
due to the technology given by the technology
or the words if you go to deep submission technologies
the length is going to decrease
that means that the intensity gain
of the muscle ancestor is going to drop
and that is exactly what we see
if we go to deposit mic on technologies
the entrance again
of the device is going to become smaller and smaller
that means that
designing operational amplifies with an high gain
will become more and more a problem
try to remember that when we talk about
sigma delta a to d conference
now a trick of course is using longer transistors
so by using longer transistors
we are able to increase the gain
of the monstrous sister
so with adverbs by using
longer transistors and the minimum feature size
we are able to increase the gain
of the transistor
but that will also result in more parasitics
and a result less speed performance
so that means we have to do a very good speed accuracy
power trade off
which will be discussed later on
in this course
however
if you go to deep submersion technologies
what is going to happen
with the length and the early voltage
well what you will see
is that if you go to deep numerical technologies
that
using the length will not help anymore for the gain
so normally we expect that if you increase the length
that the gain is going to increase
however due to certain technology
hollow doping
so if you have hollow doping in your technologies
you will see that by increasing the length
you will end up in a kind of saturation over here
so making
longer transistors will not increase the gain anymore
or with other words due to high doping avoiding
velocity saturations
they introduce a so called hallows
by introducing so hallow doping
we end up
as analog designers in a problem that we do not
air able to improve the gain by increasing the length
luckily if you go to find technology and
sheet technologies
this type of issue will vanish
and as result we are able to go to again
if you use longer transits
high gains in your topologies
that means that we have to be very careful
with the minimum feature length of the transistor
and it means also to have
very careful and how to design
high gain amplifier
which will be discussed in detail during discourse
so that brings us to the question
deeps of michael nanometer for analog circuit design
has it any advantage
the f max is not going to increase that much anymore
the power is going to increase more
compared to the f max
since that we end up with smaller area
and it transistors
more noise will pop up
especially the one of raft noise will become more
important try to remember that when I talk about the
a to d converters
and later on especially in a third day
I'm going to talk in detail also about matching
especially for d a converters matching is important
matching is a function of the area of the transistor
so if you go to deep suit micron
and we're going to scale everything
everything becomes worse
also the matching well becomes worse
or with all the words
and that's
the kind of message that I'm trying to get through
that
is that if you go to deep supermarket technologies
basically the performances are not good
but
be careful no one forbids you
to keep the same area
and going to deeps of micron
and then the story is totally different
if you do not shrink your unlock circuits
the parasitics relatively will become less
you will end up typically even more
metal in your tips mic on technologies
or without words less parasitics high speed
relatively for the same area
if you keep the same area
and you go to deep submit technology
that means that the oxide thickness becomes smaller
that means the oxide
parameter becomes better
or without words this parameter becomes better
or the noise becomes better
and what you will also see later on
if you keep the same area
the mismatch pyramid itself
due to the fact that the ox thickness becomes smaller
will also become better
or with other words
if you do not shrink
but if you go to a deepest american technology
your analog performances will become better
and this brings us to a quite important statement
we do not need deep submersion transistors
but we do need deep submersion technologies
and I do hope that you see the difference
if you shrink your technology
by going to deposit micron technology
you will end up with
not much improvement in performances
on the other hand
if you do not shrink your extra area
and you go to peacemaking technology
you will benefit a lot
and that will result in the so called speed accuracy
power thread of which I will discuss in detail
I think in the lecture of
da coverts try to remember
by going to deeps with my comp technologies
you can gain
by better matching
responsibilities
better noise performances
if you do not shrink your transistor area
on top of that
by going to deeps with my containerizes
of course you end up with more metal stacks
and by using more metal stacks
design of your structures can be much much denser
for example you see over here paper of 30 years ago
where they introduced
multi metal layer two or three metal layers
where you can basically see the improvement
in chip area due to the metal stack
of course
this can be repeated again
by more metals double triple metals and so on
so with other words not in you
what you see over here is
91
where they go from single metal to triple metal
over here they go for five metal to seven metal
the story will go on
by going to high metal stacks in the technology
allowing you to denser circuits
so the conclusion is again
deep semicon technologies have their advantage
namely less parasitics more metals available
for the same area less noise
better matching for the same area
or we do
or with other words to conclusion is we do need
supermarket and deep submittal technologies
we do not use the minimum area for ammo circuit design
fire briefly because I'm going to repeat that
in the lecture of da converters in detail
the mismatch performance the mismatch performance of
transgresses will become better
if you go to deep suit mark on technologies
and that is a big advantage by going to
deep semicon technologies
will be able to achieve better performances
and the story goes on
if you compare
all the technologies to nanometer technologies
you see that the parameter becomes bad
and paddled or with other words
by going to deep submit technologies
you're able to go to
more accurate circuits
the matching of the circuits is becoming better
this is quite important
for
the so called speed accuracy power trade off
and simply as an introduction
because I'm going to discuss that in detail
in the lecture of the a converters
you will end up in a so called speed accuracy
port of
and for simplicity let's use
simple mathematical equations
to square low relationship
the current vgs sinuosity square
now mismatch or offset is important
and the offset
has something to do with the offset
variation in the threshold
foldage or the mismatch in the threshold
and the offset variation in the better
the mobility variation
and if you use
the mathematical relationships between the spreads
of the variation in the threshold and the better
as function of the technology
it is shown that you end up with a technology perimeter
and the area of the transistor
and if you use
those mathematical relationships and you fill that
in over there
you end up in this
imported mathematical relationship over to other words
the offset foldage
in a differential pair
is given by the technology parameter
the trans conductance
the length of the transistor
the mismatch parameter
vs sinusitis
the mismatch parameter for the better
vs minus fits
not normally you are going to work
on the boundary of strong inversion
that means vs mine fit is quite small
normally this parameter is smaller than that one
so normally we can neglect this term over here
and that brings us to a quite important conclusion
what can we do as analog circuit designer
well basically this is a technology perimeter
this is a technology perimeter
if speed is important
this is given by speed just speed performance
vs minus feti
at the boundary of strong version is fixed
two hundred millivolt
so that means this is fixed
this is fixed this is fixed and this is given by your
speed performance
that the only pyramid that it can work on
in order to achieve
the accuracy is the length of the transistor
or without words
if you're off the high accuracy
and that's really the message
if you're after high accuracy
you really have to go to long transistors
and that's the only thing that you can do
again we do not need deeps with micron transistors
but we do need deeps with micron technologies
and if you blot
this mathematical relationship in a graph
you will end up in my opinion quite important
relationship
what you see over here is a plot of set voltage
of that differential pair as function of the gm
for a certain length
speed
now you know that a gm has something to do
with the bison current
or has something to do with the power drain
or without words you have the gm over here
or you have the power drain over here
this is the accuracy so the
high the lower the valley
the more the less offset the high accuracy
and what you should see is that we have a kind of
trade off between accuracy
power and speed
or you certainly see that if you're after high accuracy
that you will consume more power
and that it is
only given by the technology parameters
or with other words
once your technology is given
this
relationship is fixed
so called speed accuracy permafrost
and that can be shown mathematically
the error in the matching
has something to do with the area of the transistor
now you can increase the width of the transistor
but the width that means more power
or you can increase the length of the transistor
but the length that means speed
and as a result of that if you bring all together
you will see that the speed accuracy power to it of
accuracy square because we are talk about
statistics
speed accuracy square
overpowers
will be given by this mathematical relationship
and as you can know this
this is only technology parameter
without words the books of the technology
the fittingness
and the mismatch parameter of your technology
and this brings us to an quite important conclusion
namely that for unlock circuit design
we have a so called speed accuracy power trade off
member scale all related due to the
matching performances
for that reason
and that's quite important
and try to remember for ad and d a converters
that the design
strongly depends on the matching
and strongly depends on your technology
we will end up in a so called speed accuracy
power trade off
again
I will discuss that more in detail in the third day
and the lecture of
da converters
we will discuss in detail the speed accuracy power
trade off
this is more in channel
you can even show that
mathematically that it is exactly given by
technology Pyramids for example in an all pump
you know operational amplify
the dynamic range
is given by the
maximum voltage that you can achieve
divided by the offset voltage
and if you take that as dynamic range parameter
you will see that the speed
dynamic range accuracy
overpower in an op pump is given by
one over c ox avt square
technology parameters or without words
once your technology is given the speed accuracy
overpower is fixed
and that brings us to quite important conclusion namely
that
the power overspeed versus dynamic rage
is basically given by mismatch parameters
and if you plot for example
speed accuracy power trade of a to d converters
you see that they are not
limited to noise performances
but more linked to the matching performance
and that's the reason
why we will discuss in detail
the matching issues in this lecture
I think we will discuss it in detail
in the
lecture of the converters
now
if you plot more recent
performances of a to d converters
you will see again the speed faces power
versus the dynamic range
and you can clearly see that
the atd converters are more or less
limited to the matching performances
of course if matching is not important
or the words that you have dreaming techniques
or calibration techniques
but matching is not an issue anymore
then of course you will end up
with the norse limitation
and that's the reason why you will see some
and converters
very close to the norse limitation
for example sim delta and converters
are able to go more to that direction
be careful
but again
I'm going to talk more in detail in the lecture of
d a converters
if you go to really deep nanometer technologies
it's not only the vt which becomes important
also the better mismatch will become important
and the result extra power
will be required
so the speed accuracy power is not only given by the
threshold mismatch in the vt
but also due to the better mismatch but again
I'm going to discuss that
more detail in the lectures of da conference
and then to end the lecture
try to remember
that integrated circuit is far much more
than only the transistors
I've tried to convince you that
we have to be very careful with the source
and rain areas
but you have to also be very careful with
getting out of the chip
the packaging the stacking
look to the amount of bonds that they are using
this will result in all kind of inductance effects
interference effects
which will be discussed in the lectures of
interference effects
sometimes they use special components
bonfire components
for example to design vco circuits
or without words interconnection
it becomes an issue
careful layout
dsc all those issues are becoming important
for example if you look to an intel processor
you see a lot of extra external components popping up
mainly capacities
in order to make sure that we have no ground bounces
good power supplies
or without words
interference effects between the power supplies
is becoming quite important
in order to achieve good performances for that reason
in the last day
we are going to discuss about interference effects
about
cobbling mechanisms in order to avoid high performance
ada converters
of course
use your technology
meaning for the interconnect
use your metal stack
use your thick metal top layer
which is typically available
to distribute the power
over your circuits
but also in this microphotograph
I do hope that you see the problems popping up
by going to nanometer technologies
yes we do have a must transistor over here
but look to the amount of overhead
of positive capacitance that comes in
in the interconnection
so do not take only the intense transistor
all the external components
gate drain in gate source
drain area drain bulk area
interconnections metal connections
vias connection holes
all those things are becoming important
companies try to do their best to improve it
for example a few years ago but 10 years ago
intel introduce so called circa
micro so what they did is instead of
between the metal layers
instead of using cilia material or oxide material
they were using
vacuum and result
less positive capacities
let's power to in our high speeds
so sometimes technology
can help you in order to improve the performance
remember
electromechanics remember
the slide of the microprocessor
hundred what wine vault handed am
already 30 years ago
they claimed
electrification the time bomb of deep submit
and that's really
an important issue
the design
of your metal tracks becomes extremely important
because we are dealing with low voltage
high power that means automatically high currents
the limitations are not to transistors anymore
but the interconnection over there
result is that you have to
be very careful in the design of your metals
electromechanics big metal tracks big metal tracks
big capacity capacitance
or that means power
and that means that we indeed see
the power crisis popping up
if you go to deep submarine on technologies
the power supplies jobs
but also the leakage curds
is becoming more and more a problem
as already discussed in this lecture
if leakage problem becomes dominant
typically what happens
they will try to increase the threshold voltage
in the technology
and that will result even in more
problems for analog circuit design
but that we end up in a power crisis
meaning layout
meaning electromagnetic
hundred thirty one volt means one hundred thirty amps
that means that you have to be very careful
in the interconnection
getting out of the chip
the interconnection becomes quite imported
on top of that
deep submarine means very thin oxides
that means that we have to be very careful with
getting in and out of the chip
and that means esd born paths parasitics are coming in
a born path to day
is typically in the range of 50 by 50 micron
in the early days
hunted by hunt microns
meaning that you typically have a parasitic capacitance
in the range of last
500 femto
250 femto
if you know
that the gate source capacitance of modern transistor
is less than femto for it
you end up with a dominant party
the capacitance over here
together with easy it protects your limits dispute
for low noise amplifiers
makes these little communication systems
so again getting in and out of the chip
becomes a serious problem
speed limitation due to esd problems
due to the fact that we are going to lower voltages
that it becomes a problem
is that because you may not forget that
ese protection
is typically made out of a disorder protection network
and a diode is extra capacitive
but on top of that it's a non linear capacity
as function of the voltage that you have over here
an result of that is that you end up with a no linear
component which results in intercalation products or
ip iii values
and again if you do not know what inter
or ip iii values are
it's not important
it's these are typical parameters for telecommunication
systems
but look for example to the deck telephone system
mobile telephone the spec is plus and dm
simply using by a diode protection
you're ready very close to the speck over here
or means that you have
only a few margins left before
you are not able to achieve the performance
or the specifications anymore
simply due to the fact
that we need protections over there
that is the reason
why you see a lot of research going on in developing
new type of protection networks
minimizing the area of your bone pads
what you see over here is an
wireless rfc modes up converter topology
and can clearly see the rf
components popping up over there
trying to go to
smaller bomb paths trying to come to special
protection paths in order to void
interference effects in this time of high speed
performance components
high speed seam of the circuit design is typically not
the problem the problem is the power supply
the problem is the rising circuits
and that is what you can for example
learn on this microphotograph over here
what you see over here is an gps low north amplifier
this is amplifier over here
look to the overhead that comes in
big metal tracks to make sure
that you have a clean power supply
a lot of the couple capacitances are coming in
to make sure that you have clean rising points
or with other words
and you will see that during the lecture
and especially in the last lectures
when I talk about interference effects
add and dea design is about symmetry symmetry
symmetry decouple decouple
a lot of cheap area comes into the story for
making sure
that your biasing points are very clean and very
decoupled
pay attention to that again
we will discuss that more in detail
in one of the lectures
also
use
and know your technology
I will explain that in one of the lectures
for example norm ap versus ap technology
heavily doped versus lowly doped technology
heavily dope technology is very popular to avoid
ledge up however
heavily dope technology is very popular for
latch up however
lowly dope technologies will typically perform better
to avoid interference effects
and this can be seen for example
what you see over here is the same
adela a tod converter
and they developed that
a tod converted the same layout
in a non ap technology versus an ap technology
and this is the digital part
this is the analog part
and simply due to interference effects
between the unlock and the digital building block
it works about three db better performance
in a lowly doped technology
compared to an half doped technology
again these are interference effects
which will be discussed in detail in the
lost lectures
about interference effects in analog circuit design
over the words
not only the minimum feature size is important
also the technology ap
non ap heavily supped lowly supped
also for digital circuit designers
this becomes important
what you see over here is a metal line resistance
and interconnection is important
for digital circuit design
as function of the speed
and this is one he hurts this is 10 he hearts
and what you should see is that
the problem that we are facing is
and that's one of the reasons why you do not see much
processes high
then 10 he hearts
is you to do the interconnect
the interconnect
is not a metal wire anymore
it will
act as a more inductive interconnection over there
on the other hand if you go to
lowly dough materials
you see that we are able to avoid this type of problems
again I'm going to discuss this type of issues
more in detail in the lectures of interference effects
but again the messages
for an analog circuit design is far much more than
only the entrance transistor
the type of material heavily doped lowly doped
the kind of metal stack
the kind of drain areas source areas
all those issues are becoming important
to enter lecture
deep submarine on technologies
yes
deep american technologies is way to go
we do not always use the deeps of micron transistors
the major difference is that if you keep the same area
matching will become better in the new technologies
you have more metal stacks in your technologies
typically we will end up with
lowly dope technologies in dipsomaniac technologies
and result is that you will end up
with better performed circuits
bottom line of the discussion
do we need deeps with micron transistors
no but we do need deeps with micron technologies
and by that I'm going to anti lecture
and then in the next lecture
we will use this type of things to discuss
the circuits I will start off with
co delta a to d converters in the next lectures
thank you very much