We talked about PTEs, PDEs, and the like. Here's what that looks
like for x64. We have a bunch of bits here. Notice that there are
some bits here which are more important than others, and I would
like to talk about them here.
So first thing is that we have the valid bit. So here's the valid bit,
and the valid bait indicates whether that entire entry really should be
examined and looked at by the processor.
If the valid bit is 1, then what we see here is the
thing that the processor is looking at.
If the value bit is 0,
the CPU doesn't make forward progress, but instead raises a page
fault exception. And then we have the PFN.
The PFN is the page frame number.
That's essentially the value that we need to multiply by the size of a
page to see where the next item is in physical memory.
So, for PTE, for example, these 36 bits,
if you add the other 12 bits coming from the offset,
that's exactly 48 bits pointing to some address in physical memory, which is
also the maximum that is supported by those processors,
not just in the future address space, but also in the physical address space,
no more than 256 TB.
And then you might recall,
we mentioned the fact that there are large pages also that are supported.
So what is the benefit of a large page from a hardware perspective?
The benefit is that instead of having a 4k page,
you now have 2 MB page size so that you don't need page tables, and a single
entry can map an entire 2 MB range in physical memory.
I'll discuss some of the downsides of large page files in
the last module in this course. However,
the benefit is mostly with the Translation Lookaside Buffer
cache, the TLB cache, because now a single entry in the cache
maps 2 MB in size instead of just 4 KB.
And so the large page bit here tells the CPU not to move further,
but consider the rest of what remains in the bits for
the non‑used address as the offset.
So why is the page size 2 MB? Let me go back to the previous slide
for a moment and see the full translation here.
You'll notice that if we dismissed with the page tables, then we get 12 bits,
plus 9 bits, 21 bits, and 21 bits is exactly 2 MB in size.
So this is where this large page size is coming from.
And for a huge page, by the way,
which I also mentioned is supported by Intel's processors, is sized with 1 GB.
So again,
where can we find 1 GB here, and now it's perhaps obvious that
1 GB is dismissing with the page directories also, and we get
12 bit plus 9 bits plus 9 bits, that's exactly 30 bits, which
is exactly 1 GB in size.
So with a huge page, we have even a better usage of the
Translation Lookaside Buffer. Of course,
there is a downside, which I'll discuss in the last module in this
course. So that would be the large page size bit.
You can see that there are some reserved bits here,
which means that there's still room to increase that scheme,
and with PML level 5 with the new scheme that Intel supports
today, if you add 9 more bits,
there's still a little bit of free bits there in order to even support more memory in the future.